MVLC_100... is intended for MVLC with large FPGA (standard)
MVLC_45...  for small FPGA. For very few devices of first series

MVLC_45 no longer supported, not enough resources for new features

MVLC_100/45_FW0012 trigger_io updates (daq_start)

FW0015 event stamper with output buffer implemented.
	6010 irq_level0[2:0]  // For threshold 0;  1 to 7; 0 = off
	6012 irq_level1[2:0] 	 // For Threshold 1;  Internal IRQ, 
	603A start_events 	 // accumulate time stamps
	601E irq_event_threshold0[15:0] // max 4k events 
	6018 irq_event_threshold1[15:0] // max 4k events
	6016 max_transfer_data[15:0] // number of time stamps transfered in one BLT access

FW0017 DSO built in 
	fixed strobed LUT bugs: 
	8x universal utils: when used as IRQ inputs

FW0018 DSO built in, scans NIM inputs, 6x IRQ inputs 
	  Collision bug Counter read and Counter0-FIFO read fixed.

FW0020 VME bus timeout increased from 1.6us to 16us
	Multi crate synchronisation implemented in Hardware
	Some new stack commands implemented (still undocumented)
FW0021 Multicrate features implemented, CR/CSR space addressing for 	some modules (am codes extended). Timing optimisations
FW0022 Multicrate synchronisation improved; 
	 Error capture at VME read/write -> blink signal at front LEDs
FW0023 extend signal to IRQ translation table to 8 entries (0x7000 to 	0x701E)
FW0024 new Reg 0x7020 : assign unassigned signals to specified 	internal IRQ
	Fix Trig IO glitches (from FW0022)
FW0026 minor fixes, 
	max Stack size increased from 1kWords to 2kWords.
	read/write with Berr response -> fixed error message.
FW0027 fixed DHCP bug: ping while DHCP is active could set the IP. 
	-> no host name was registered in DHCP server.
FW0028 Fixed BLT bug. BLT could break without Berr
	New Feature: 2ESST readout (2ESSTS: swapped words); For more than 128 cycles, several blocks are requested. If requested number of words are not sent -> breaks. 2ESST instruction is of type "FIFO": multi blocks start from same address.
FW0029 Fix ESST speed parameter
	 Fix timing problem when AS* is only 45ns inactive between cycles
FW0030 Fix read16/32 with Berr: now adds error word and continues stack. 
Known problem: 2ESST readout of CAEN v1742 breaks randomly.
FW0031 Fix edge overflow problems with DSO (digital signal oscilloscope), now 32 edges per wave can be displayed. mvme was adapted for DSO display. Reduce glitches on IRQ signal inputs.

FW0032 solved some ESST problems. Solved random (1/3000) bad first word in data.

FW0033 creates backplane clock also when not synchronised.
	recovers from not sync when sync clock appears again.
FW0035 ESST fix(loss of word at Speed 320, >370words)
	 Daq by default off (reg 0x1300 = 0)
FW0036 implement programming of MVLC firmware via USB/Ethernet
	VME stack poll command now runs over max 64k cycles.
	Fixed event time stamper FIFO (Trig-IO)
	new cmds for memory read of internal and VME address space with BLT, MBLT, ESST, BDread16/32: 
	  CMD_VME_READ_INC
	  CMD_VME_READ64_SWAP_INC
FW0037 	Crate ID in UDP header0 for all output channels; fix DHCP bug with crate_id high bit
	increased number of stacks from 8 to 16 stacks.
	all stacks can be triggered by any of 4 new timers outside trig_io. Periode in ms